The present disclosure relates generally to testing a circuit design, and more specifically to testing a circuit design using a programmable emulation tool having improved performance.
Verification of Very Large Scale Integrated (VLSI) circuits is important to the success of any modern VLSI product. Verification typically involves running a large number of tests on the circuit by simulating the circuit on a state-of-the-art computer system. In the past decade, it has often become intractable to conduct such tests on general purpose computing equipment for reasons of poor performance and capacity. Some VLSI manufacturers have shifted to running tests on specialized Configurable Hardware Logic (CHL). This method is called hardware emulation, hereinafter also referred to as emulation.
In emulation, the VLSI design is mapped into a set or multitude of CHLs, which together exhibit the behavior of the mapped circuit design. The CHLs may be Field Programmable Logic Arrays (FPGAs), for example. Emulation presents several challenges:
1. Splitting the design onto the CHLs, hereinafter also referred to as “partitioning”.
2. Routing wires from one part of the design that is mapped on one CHL, e.g. CHL A, to another part of the design that is mapped on a different CHL, e.g. CHL B, hereinafter also referred to as “routing”. This may involve several hops across other intermediate CHLs, e.g. not CHL A or B, because of physical connectivity constraints; not all CHL pairs, e.g. CHL A, B, may be directly connected to one another.
3. Assigning specific design wires to specific physical CHL communication ports (called sockets), hereinafter also referred to as the “pin assignment”.
A complication of pin assignment is that more than one wire may map onto the same socket because the number of physical sockets is typically smaller than the number of wires to be assigned. One solution to this problem utilizes time division multiplexing (TDM) hereinafter also referred to as “multiplexing”. TDM divides a larger time unit (e.g., 1 second) into multiple smaller time units (e.g., 1/100 of a second). At each small time unit data is transmitted for a different virtual wire. The wires assigned to the TDM time slots are hereinafter also referred to as “virtual wires”. The sender and receiver circuits of signals on virtual wires coordinate to associate virtual wires with TDM time slots.
Thus pin assignment presents a twofold challenge: assigning the wires to sockets, and forming a time multiplexing hardware infrastructure in the programmable devices, e.g. the set of FPGAs. The time multiplexing may be implemented by a set of mapped multiplexer circuits. The challenges of wire assignment to sockets and wire assignment to TDM time slots are coupled, because addressing the second challenge introduces further constraints on the possible assignments available to address the first challenge and directly affects emulator speed because the number of sockets is constrained by the hardware. Therefore, there is a need to assign wires to sockets such that emulator speed is improved.